1. Field of the Invention
The present invention relates to a voltage controlled ring oscillator suitable for the application to a PLL circuit, and more particularly to improvement for suppressing the influence of the fluctuation of a source voltage on the cycle (period) of an output clock signal.
2. Description of the Background Art
FIG. 29 is a circuit diagram showing the structure of a voltage controlled ring oscillator (VCO) according to the prior art which has been published in U.S. Pat. No. 5,075,640 which is the background of the present invention. As shown in FIG. 29, a VCO 151 comprises current controlled delay circuits 26.1 to n (n is an odd number) and a current control circuit 121.
A PMOS 21.k, a PMOS 22.k, an NMOS 24.k and an NMOS 25.k included in a current control delay circuit 26.k (k=1 to n) are sequentially connected, in series, from a high potential side power line 11 to a ground side power line 12. The gate electrode of the PMOS 22.k is connected to that of the NMOS 24.k so that the PMOS 22.k and the NMOS 24.k form an inverter 20.k. Inverters 20.1 to n are cascade-connected cyclically (annularly) in such a manner that the output of a stage is connected to the input of the next stage.
The current control circuit 121 includes PMOSs 27 and 28 and NMOSs 29 and 30. An input terminal 13 for inputting an input voltage signal VIN is connected to the gate electrode of the NMOS 30. A current having a magnitude which is proportional to the magnitude of the input voltage signal VIN flows in the NMOS 30.
The PMOS 28 whose gate and drain electrodes are short-circuited is connected to the NMOS 30 in series. Furthermore, the PMOS 28, the PMOS 27 and PMOSs 21.1 to n form a current mirror circuit. For this reason, a current having a magnitude which is proportional to that of the current flowing in the NMOS 30 flows in the PMOS 27 and the PMOSs 21.1 to n.
The NMOS 29 whose gate and drain electrodes are short-circuited is connected to the PMOS 27 in series. Furthermore, the NMOS 29 and NMOSs 25.1 to n form a current mirror circuit. For this reason, a current having a magnitude which is proportional to that of the current flowing in the NMOS 30 also flows in the NMOSs 25.1 to n. Thus, the current control circuit 121 serves to control the PMOSs 21.1 to n and the NMOSs 25.1 to n so as to cause a current having a magnitude which is proportional to the magnitude of the input voltage signal VIN to flow. The PMOSs 21.1 to n and the NMOSs 25.1 to n function as current sources for the inverters 20.1 to n.
When signals having the low and high levels are inputted, each of the inverters 20.1 to n outputs signals having the inverted levels after a delay time. The delay time in which the output rises from the low level to the high level is inversely proportional to the magnitude of the current which flows in the PMOSs 21.1 to n. The delay time in which the output falls from the high level to the low level is inversely proportional to the magnitude of the current which flows in the NMOSs 25.1 to n.
The number of the inverters 20.1 to n is odd. In addition, the inverters 20.1 to n are connected like a ring. For this reason, the low level and the high level are alternately propagated every stage to perform oscillation. Furthermore, the cycle (or period) of the oscillation is the total of the delay values of the inverters 20.1 to n. In particular, if the delay values of rise and fall are equal to each other, the cycle of the oscillation is 2 n times as much as each delay value.
More specifically, the inverters 20.1 to n oscillate at a frequency which is proportional to the input voltage signal VIN. The output of the current controlled delay circuit 26.n which oscillates is fetched as a clock signal VOUTC to the outside through an output terminal 14 connected to the current controlled delay circuit 26.n.
The VCO 151 according to the prior art has the above-mentioned structure. Therefore, there is a problem that the delay times of the inverters 20.1 to n are greatly influenced by the potential of the high potential side power line 11, that is, a potential difference between the high potential side power line 11 and the ground side power line 12. FIG. 30 is a graph typically showing the waveform of the clock signal VOUTC to explain the above-mentioned problem.
Each of the PMOSs 21.1 to n and the NMOSs 25.1 to n which belong to the current controlled delay circuits 26.1 to n merely changes the amount of a drain-source current (main current) thereof according to the value of the input voltage signal VIN. For this reason, the potential of an output of each of the inverters 20.1 to n transits between the potential of the ground side power line 12 and a potential VDD of the high potential side power line 11 as shown in FIG. 30. Consequently, the delay time of each of the inverters 20.1 to n is varied under the influence of the potential VDD of the high potential side power line 11.
As a result, the straight line of a threshold voltage VT which is a reference value to distinguish the clock signal VOUTC into the high and low levels and the curve of the clock signal VOUTC do not always intersect at regular time intervals but the cycle of intersection fluctuates. In other words, the VCO 151 has had a problem that the fluctuation of the cycle is caused to the clock signal VOUTC by the fluctuation of the potential VDD, that is, a period jitter appears. In an example of FIG. 30, a cycle T1 and a cycle T2 have the relationship of T1&lt;T2. It has been known that the period jitter appears especially remarkably when the cycle of the fluctuation of the potential VDD approximates the cycle of the clock signal VOUTC.